LVDS 18-Bit Color Flat Panel Display (FPD) Link

The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDs (Low Voltage Differential Signaling) data streams. A phase-locked transmit Clock is transmitted in parallel with the data streams over a fourth LVDs link. Every cycle of the transmit Clock 21 bits of input data are sampled and transmitted. The DS90CF562 receiver converts the LVDs data streams back into 21 bits of CMOS/TTL data. At a transmit Clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD Timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per LVDs data channel. Using a 40 MHz Clock the data throughput is 105 Megabytes per second. These devices are offered with falling edge data strobes for convenient Interface with a variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL Interfaces
By National Semiconductor Corporation
DS90CF562 's PackagesDS90CF562 's pdf datasheet

DS90CF562 Pinout, Pinouts
DS90CF562 pinout,Pin out
This is one package pinout of DS90CF562,If you need more pinouts please download DS90CF562's pdf datasheet.

DS90CF562 Application circuits
DS90CF562 circuits
This is one application circuit of DS90CF562,If you need more circuits,please download DS90CF562's pdf datasheet.

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