28-bit Channel Link - National Semiconductor

The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDs (Low Voltage Differential Signaling) data streams. A phase-locked transmit Clock is transmitted in par- allel with the data streams over a fifth LVDs link. Every cycle of the transmit Clock 28 bits of input data are sampled and transmitted. The DS90CR282 receiver converts the LVDs data streams back into 28 bits of CMOS/TTL data. At a trans- mit Clock frequency of 40 MHz, 28 bits of TTL data are trans- mitted at a rate of 280 Mbps per LVDs data channel. Using a 40 MHz Clock the data throughput is 1.12 Gbit/s (140 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data bus and one Clock up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 Clock pair and a minimum of one By National Semiconductor Corporation
DS90CR281 's PackagesDS90CR281 's pdf datasheet
DS90CR282




DS90CR281 Pinout, Pinouts
DS90CR281 pinout,Pin out
This is one package pinout of DS90CR281,If you need more pinouts please download DS90CR281's pdf datasheet.

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