28-Bit Channel-Link - 66 MHz

The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDs (Low Voltage Differential Signaling) data streams. A phase-locked transmit Clock is transmitted in parallel with the data streams over a fifth LVDs link. Every cycle of the transmit Clock 28 bits of input data are sampled and transmitted. The DS90CR284 receiver converts the LVDs data streams back into 28 bits of CMOS/TTL data. At a transmit Clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDs data channel. Using a 66 MHz Clock the data throughput is 1.848 Gbit/s (231 Mbytes/s).
The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data bus and one Clock up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 Clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.
The 28 CMOS/TTL inputs CAN support a variety of signal combinations. For example, 7 4-bit nibbles or 3 9-bit (byte + parity) and 1 control.
By National Semiconductor Corporation
DS90CR283 's PackagesDS90CR283 's pdf datasheet

DS90CR283 Pinout, Pinouts
DS90CR283 pinout,Pin out
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