3-40MHz DC- Balanced 24-Bit LVDS DeserializerThe DS99R105 DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDs serial stream with
embedded Clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating
the skew problems between parallel data and Clock paths. It saves system cost by narrowing data paths that in turn reduce
PCB layers, cable width, and connector size and pins.
The DS99R105 DS99R106 incorporates LVDs signaling on the high-speed I/O. LVDs provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. By National Semiconductor Corporation |
Part | Manufacturer | Description | Datasheet | Samples | |
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DS99R106SQX/NOPB | Texas Instruments | 3-40MHz DC- Balanced 24-Bit LVDS Deserializer 48-WQFN 0 to 70 | |||
DS99R106VS/NOPB | Texas Instruments | 3-40MHz DC- Balanced 24-Bit LVDS Deserializer 48-TQFP 0 to 70 | |||
DS99R106SQ/NOPB | Texas Instruments | 3-40MHz DC- Balanced 24-Bit LVDS Deserializer 48-WQFN 0 to 70 | |||
DS99R106VSX/NOPB | Texas Instruments | 3-40MHz DC- Balanced 24-Bit LVDS Deserializer 48-TQFP 0 to 70 | |||
SERDES05-40USB | Texas Instruments | Evaluation Kit for DS99R105 DS99R106 FPD-Link II Serializer and Deserializer Chipset |
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DS99R106 Pb-Free | DS99R106 Cross Reference | DS99R106 Schematic | DS99R106 Distributor |
DS99R106 Application Notes | DS99R106 RoHS | DS99R106 Circuits | DS99R106 footprint |