Digital Fir Filter Design Using The Msp430f16x

This application report describes an FIR Filter implementation using the MSP430F16x and the MSP430F161x family devices. The complete Filter algorithm is executed by the 3-channel DMA peripheral and the hardware multiplier peripheral. These modules are used in conjunction with the allocated coefficient table in the program memory and the circular data Buffer space dedicated in the RAM of the device. The hardware multiplier performs the signed multiply-and-accumulate (MACS) operations in the algorithm. The integrated Analog-to-digital converter, ADC12, is used for data acquisition. The software for the Filter is written in such a way that all the Filter parameters including the coefficients are loaded into a look-up table. This allows the same Filter program to be used for any type of FIR Filter implementation such as high-pass, low-pass, band-pass and band-reject Filters The integrated digital-to-analog converter, DAC12, CAN be used for converting the Filter output back into the Analog domain if required.
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