4M X 32 Bit Synchronous DRAM (SDRAM)

The EM639325 SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous Interface (all signals are registered on the positive edge of the Clock signal, CLK). Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM639325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By Etron Technology Inc.
EM639325 's PackagesEM639325 's pdf datasheet
EM639325TS-6G TSOP




EM639325 Pinout, Pinouts
EM639325 pinout,Pin out
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