Cyclone FPGA Family Data Sheet

The Cyclone field programmable Gate array family EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 is based on a 1.5-V, 0.13-m, all-layer copper SRAM process, with densities up to 20,060 Logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) Interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDs at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. By Altera Corporation