Stratix GX Device Family Data Sheet

The Stratix GX family of devices EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G is Alteras second FPGA family to combine high-speed serial transceivers with a scalable, high-performance Logic array. Stratix GX devices include 4 to 20 high-speed transceiver channels, each incorporating Clock data recovery (CDR) technology and embedded SERDES capability at data rates of up to 3.1875 gigabits per second (Gbps). These transceivers are grouped by four-channel transceiver blocks, and are designed for low power consumption and small die size. The Stratix GX FPGA technology is built upon the Stratix architecture, and offers a 1.5-V Logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable, high-performance architecture makes Stratix GX devices ideal for high-speed Backplane Interface chip-to-chip, and Communications protocol-bridging applications. By Altera Corporation