FBL2041; FBL2041I 3.3V BTL 7-bit Futurebus+ Transceiver (standard A-port)

FBL2041; FBL2041I 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port),The FBL2041 FBL2041I is a 7-bit bidirectional BTL transceiver and is intended to provide the electrical Interface to a high performance wired-OR bus. The FBL2041 is an inverting transceiver. The B-port drivers are Low-capacitance Open Collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The FBL2041 FBL2041I is pin and function compatible with FB2041 but operates at a 3.3V supply voltage, greatly reducing power consumption. The B-port Interfaces to "Backplane Transceiver Logic" (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series Diode on the drivers. BTL also provides incident wave switching, a necessity for high performance Backplanes There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1, output drivers for bits 1-2-3 are enabled with OEA2/OEB2 and output drivers for bits 4-5-6 are enabled with OEA3/OEB3. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEAn goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEAn goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 1.3V. The B-port has an output enable, OEB0, which affects all seven drivers. When OEB0 is High and OEBn is Low the output driver will be enabled. When OEB0 is Low or if OEBn is High, the B-port drivers will be inactive and at the level of the Backplane signal. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while VCC is Low. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The Logic GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. JTAG boundary scan functionality is provided as an option with signals TMS, TCK, TDI and TDO. When this option is not present, TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally.
By NXP Semiconductors
FBL2041 's PackagesFBL2041 's pdf datasheet

FBL2041 Pinout, Pinouts
FBL2041 pinout,Pin out
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