8K-Bit Standard 2-Wire Bus

The FM24C08U FM24C09U devices are 8192 bits of CMOS non-volatile electrically erasable memory. These devices conform to all speci- fications in the Standard IIC 2-wire protocol. They are designed to minimize device pin count and simplify PC board layout require- ments. The upper half (upper 4Kbit) of the memory of the FM24C09U CAN be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This Communications protocol uses Clock (SCL) and DATA I/O (SDA) lines to synchronously Clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by the Fairchild family in 2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs In order to implement higher EEPROM memory densities on the IIC bus, the Extended IIC protocol must be used. (Refer to the FM24C32 or FM24C65 datasheets for more informa- tion.) Fairchild EEPROMs are designed and tested for applications requir- ing high endurance, high reliability and low power consumption. By Fairchild Semiconductor
FM24C08U 's PackagesFM24C08U 's pdf datasheet

FM24C08U Pinout, Pinouts
FM24C08U pinout,Pin out
This is one package pinout of FM24C08U,If you need more pinouts please download FM24C08U's pdf datasheet.

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