Zero Delay Clock Multiplier

Zero Delay Clock Multiplier FMS7951 is a high speed, zero delay, low skew Clock Driver It uses Phase locked loop technology to generate frequencies up to 175 MHz. REF_SEL allows selection between PECL input or TCLK a CMOS Clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will by pass the Phase locked loop In this mode, FMS7951 will be in Clock Buffer mode where any Clock applied to TCLK will be divided down to the four out- put banks. This is ideal for system diagnostic test. When PLL_EN is HIGH, the PLL is enabled, and any Clock applied to TCLK will be locked in both phase and frequency to FBIN. PECL_CLK is activated when REF_SEL is high. FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP. By Fairchild Semiconductor
FMS7951 's PackagesFMS7951 's pdf datasheet

FMS7951 Pinout, Pinouts
FMS7951 pinout,Pin out
This is one package pinout of FMS7951,If you need more pinouts please download FMS7951's pdf datasheet.

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