This device contains two independent positive-edge-triggered D-type Flip-Flops A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input ...
This device contains two independent positive-edge-triggered D-type Flip-Flops A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input ...
This is a single positive-edge-triggered D-type flip-flop SN74AUP1G79 . When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a ...
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock\'s (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data ...
This single positive-edge-triggered D-type flip-flop SN74AUC1G79 is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation ...
CD4013B consists of two identical, independent data-type Flip-Flops Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and , by connecting Q output to the data ...
Cd40174B consists of six identical ?D?-type Flip-Flops having independent DATA inputs. The CLOCK and CLEAR inputs are common to all six units. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All sic Flip-Flops are ...
Cd40175B consists of four identical D-type Flip-Flops Each flip-flop has an independent DATA D input and complementary Q and Q outputs. The CLOCK and CLEAR inputs are common to all Flip-Flops Data are transferred to the Q outputs on the positive-going ...
The CD74AC174 is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input and is designed for 1.5-V to 5.5-V VCC operation. Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the ...
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the ...
The ?AC273 and ?ACT273 devices are octal D-type Flip-Flops with reset that utilize advanced CMOS logic technology. Information at the D input is transferred to the Q output on the positive-going edge of the clock pulse. All eight Flip-Flops are controlled by a ...
The CD74AC74 dual positive-edge-triggered devices are D-type Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the ...
The CD74ACT174 devices are positive-edge-triggered D-type Flip-Flops with a direct clear (CLR) input and are designed for 4.5-V to 5.5-V VCC operation. Information at the data (D) inputs that meets the setup time requirements is transferred to the ...
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the ...
The CD74ACT273 and CD74ACT273 devices are octal D-type Flip-Flops with reset that utilize advanced CMOS logic technology. Information at the D input is transferred to the Q output on the positive-going edge of the clock pulse. All eight Flip-Flops are ...
The CD74ACT74 dual positive-edge-triggered devices are D-type Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the ...
The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data ...
The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode ...
The ?HC174 and ?HCT174 are edge triggered Flip-Flops which utilize silicon gate CMOS circuitry to implement D-type Flip-Flops They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave Flip-Flops with ...
The ?HC175 and ?HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ...
The CD74HC273 and CD74HC373 high speed octal D-Type Flip-Flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits. Information at the D inputis ...
The CD74HC377 and CD74HCT377 are octal D-type Flip-Flops with a buffered clock (CP) common to all eight Flip-Flops All the Flip-Flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E) is Low. ...
The ?HC74 and ?HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop ...
The CD74HCT174 and ?HCT174 are edge triggered Flip-Flops which utilize silicon gate CMOS circuitry to implement D-type Flip-Flops They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops ...
The CD74HCT175 and ?HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ...
The ?HC273 and ?HCT273 high speed octal D-Type Flip-Flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits. Information at the D inputis transferred ...
The ?HC377 and ?HCT377 are octal D-type Flip-Flops with a buffered clock (CP) common to all eight Flip-Flops All the Flip-Flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E) is Low. ...
The CD74HCT74 and ?HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This ...
The FCT273T devices consist of eight edge-triggered D-type Flip-Flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR) inputs load and reset all Flip-Flops simultaneously. These devices are edge-triggered registers. ...
The FCT377T devices have eight triggered D-type Flip-Flops with individual data (D) inputs. The common buffered clock (CP) inputs load all Flip-Flops simultaneously when the clock-enable (CE) input is low. The register is fully edge triggered. The state of ...
This single positive-edge-triggered D-type flip-flop SN74LVC1G79 is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the ...
The SN74ABT273 are 8-bit positive-edge-triggered D-type Flip-Flops with a direct clear () input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators. Information at the data (D) inputs ...
These 8-bit positive-edge-triggered D-type Flip-Flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators. Data (D) input information that meets the setup time ...
The ?AC74 devices are dual positive-edge-triggered D-type Flip-Flops A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) ...
The SN74ACT74 dual positive-edge-triggered devices are D-type Flip-Flops A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the ...
The SN74AHC174 devices are positive-edge-triggered D-type Flip-Flops with a direct clear (CLR) input and are designed for 2-V to 5.5-V VCC operation. Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs ...
These circuits SN74AHC273 are positive-edge-triggered D-type Flip-Flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) ...
The SN74AHC74 dual positive-edge-triggered devices are D-type Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the ...
The SN74AHC74Q dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the ...
These positive-edge-triggered D-type Flip-Flops SN74AHCT174 have a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock ...
These devices SN74AHCT273 are positive-edge-triggered D-type Flip-Flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) ...
The SN74AHCT74 dual positive-edge-triggered devices are D-type Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the ...
The SN74AHCT74Q is a dual positive-edge-triggered D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) ...
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The SN74ALS174 and SN74ALS174 feature complementary outputs from each flip-flop. Information at the data (D) inputs ...
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The SN74ALS175 and SN74ALS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs ...
These octal positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear () input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the ...
These devices contain two independent positive-edge-triggered D-type Flip-Flops A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input ...
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The SN74AS174 and ?AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs ...
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The ?ALS175 and SN74AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs ...
These devices contain two independent positive-edge-triggered D-type Flip-Flops A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input ...
This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the ...
This positive-edge-triggered flip-flop SN74F175 utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR) input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge ...
The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The SN74F377A features a latched clock enable () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the ...
These devices contain two independent positive-edge-triggered D-type Flip-Flops A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input ...
These positive-edge-triggered D-type Flip-Flops have a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering ...
These positive-edge-triggered D-type Flip-Flops have a direct clear (CLR) input. The SN74HC175 devices feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs ...
These circuits are positive-edge-triggered D-type Flip-Flops SN74HC273 with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) ...
This circuit is a positive-edge-triggered D-type flip-flop SN74HC273-Q1 with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) ...
These devices are positive-edge-triggered octal D-type Flip-Flops with an enable input. The SN74HC377 devices are similar to the ?HC273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) ...
The SN74HC74 devices contain two independent D-type positive-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data ...
The SN74HC74 device contains two independent D-type positive-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data ...
These devices are positive-edge-triggered D-type Flip-Flops with a common enable input. The SN74HCT273 devices are similar to the SN74HCT273 devices, but feature a common clear enable (CLR) input instead of a latched clock. Information at the data (D) ...
These devices are positive-edge-triggered D-type Flip-Flops The ? SN74HCT377 devices are similar to the \'HCT273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) inputs meeting the setup ...
The ?HCT74 devices contain two independent D-type positive-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at ...
These monolithic, positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the \'175, \'LS175, and \'S175 feature complementary outputs from each flip-flop. Information at the D ...
These monolithic, positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the \'175, \'LS175, and \'S175 feature complementary outputs from each flip-flop. Information at the D ...
These monolithic, positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going ...
These monolithic, positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The \'LS377, \'LS378, and \'LS379 devices are similar to \'LS273, \'LS174, and \'LS175, respectively, but feature a common ...
These monolithic, positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The \'LS377, \'LS378, and \'LS379 devices are similar to \'LS273, \'LS174, and \'LS175, respectively, but feature a common ...
These devices contain two independent D-type positive-edge-triggered Flip-Flops A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input ...
The \'LV174A devices are hex D-type Flip-Flops designed for 2-V to 5.5-V VCC operation. These devices are monolithic positive-edge-triggered Flip-Flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements ...
The \'LV175A devices are quadruple D-type Flip-Flops designed for 2-V to 5.5-V VCC operation. These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup ...
The SN74LV273A devices are octal D-type Flip-Flops designed for 2-V to 5.5-V VCC operation. These devices are positive-edge-triggered Flip-Flops with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is ...
These dual positive-edge-triggered D-type Flip-Flops SN74LV74A are designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR ...
This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive ...
The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. A low level at the preset (PRE) or ...
The SN74LVC74A-Q1 dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR ...
These octal D-type Flip-Flops SN74LVTH273 are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The ?LVTH273 devices are positive-edge-triggered Flip-Flops with a ...
These monolithic, positive-edge-triggered Flip-Flops SN74S174 utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the \'175, \'LS175, and \'S175 feature complementary outputs from each flip-flop. Information at ...
These monolithic, positive-edge-triggered Flip-Flops SN74S175 utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the \'175, \'LS175, and \'S175 feature complementary outputs from each flip-flop. Information at ...
These devices contain two independent D-type SN74S74 positive-edge-triggered Flip-Flops A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the ...
The 74AC16374 are 16-bit edge-triggered D-type Flip-Flops with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional ...
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The SN54ACT16374 and 74ACT16374 are 16-bit edge-triggered D-type Flip-Flops with 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, ...
These 18-bit Flip-Flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working ...
The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit Flip-Flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q ...
The RCA-CD54/74AC374 and CD54/74AC534 and the CD54/74ACT374 and CD54/74ACT534 octal D-type, 3-state, positive-edge triggered Flip-Flops use the RCA ADVANCED CMOS technology. The eight Flip-Flops enter data into their registers on the LOW-to-HIGH transition of ...
The RCA-CD54/74AC374 and CD54/74AC534 and the CD54/74ACT374 and CD54/74ACT534 octal D-type, 3-state, positive-edge triggered Flip-Flops use the RCA ADVANCED CMOS technology. The eight Flip-Flops enter data into their registers on the LOW-to-HIGH transition of ...
The RCA-CD54/74AC564 and CD54/74AC574 and the CD54/74ACT564 and CD54/74ACT574 octal D-type, 3-state, positive-edge-triggered Flip-Flops use the RCA ADVANCED CMOS technology. The eight Flip-Flops enter data into their registers on the LOW-to-HIGH transition of ...
The RCA-CD54/74AC374 and CD54/74AC534 and the CD54/74ACT374 and CD54/74ACT534 octal D-type, 3-state, positive-edge triggered Flip-Flops use the RCA ADVANCED CMOS technology. The eight Flip-Flops enter data into their registers on the LOW-to-HIGH transition of ...
The RCA-CD54/74AC564 and CD54/74AC574 and the CD54/74ACT564 and CD54/74ACT574 octal D-type, 3-state, positive-edge-triggered Flip-Flops use the RCA ADVANCED CMOS technology. The eight Flip-Flops enter data into their registers on the LOW-to-HIGH transition of ...
The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable ...
The ?HC173 and ?HCT173 high speed three-state quad Dtype Flip-Flops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power ...
The CD74HC374 , HCT374, HC574, and HCT574 are octal D-type Flip-Flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered Flip-Flops enter data into their registers on the LOW to HIGH transition of clock (CP). The ...
The ?HC534, ?HCT534, ?HC564, and ?HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS technology. They possess the low power consumption of stan-dard CMOS integrated circuits, as well as the ability to drive 15 LSTTL loads. Due to ...
The ?HC534, ?HCT534, ?HC564, and ?HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS technology. They possess the low power consumption of stan-dard CMOS integrated circuits, as well as the ability to drive 15 LSTTL loads. Due to ...
The ?HC374, ?HCT374, ?HC574, and ?HCT574 are octal D-type Flip-Flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered Flip-Flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output ...
The ?HC173 and ?HCT173 high speed three-state quad Dtype Flip-Flops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power ...
The ?HC374, ?HCT374, ?HC574, and ?HCT574 are octal D-type Flip-Flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered Flip-Flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output ...
