GAL Data Sheets Low Voltage E2 CMOS PLD Generic Array Logic™

The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C CAN Interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2 CMOS process, which com- bines CMOS with Electrically Erasable (E2 ) floating Gate technology. High speed erase times (<100ms) allow the devices to be repro- grammed quickly and efficiently. The 3.3V GAL16LV8 uses the same industry standard 16V8 archi- tecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. By Lattice Semiconductor Corp.
GAL16LV8 's PackagesGAL16LV8 's pdf datasheet
GAL16LV8D-3LJ PLCC
GAL16LV8D-5LJ PLCC
GAL16LV8C-7LJ PLCC
GAL16LV8C-10LJ PLCC
GAL16LV8C-15LJ PLCC
GAL16LV8D-3LJN PLCC
GAL16LV8D-5LJN PLCC
GAL16LV8C-7LJN PLCC
GAL16LV8C-10LJN PLCC
GAL16LV8C-15LJN PLCC




GAL16LV8 Pinout, Pinouts
GAL16LV8 pinout,Pin out
This is one package pinout of GAL16LV8,If you need more pinouts please download GAL16LV8's pdf datasheet.

GAL16LV8 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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GAL16LV8 Application Notes GAL16LV8 RoHS GAL16LV8 Circuits GAL16LV8 footprint
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