Fabricated in 0.7 micron CMOS technology, the GC3011 chip is a general purpose digital resampler chip designed to accurately reduce the sample rate of the input data stream by a fractional amount ranging from 1.0 down to 0.25. The chip includes an interpolation control block, a multi-chip synchronization and offset circuit, a 15 tap interpolation Filter a 16 word output FIFO memory, an output Clock Generator and an interpolation ratio rate-lock loop (RLL) circuit. In addition, an output multiplexor circuit allows the user to by-pass the FIFO and output the resampled samples directly. A control Interface allows the user to set the resampling modes, resampling rate and output clocking modes. The multi-chip sync and offset circuit allows multiple GC3011 chips to be synchronized in a master/slave configuration. The offset portion of the circuit allows each chips interpolation delay to be offset by a fixed amount relative to the other chips. The GC3011 chip accepts input rates up to 70 MHz. The chip CAN operate in a fixed resampling mode where the user specifies the desired output rate, or the chip CAN be configured to adapt the resampled rate to match an externally provided output Clock The resampled data CAN be output synchronous to the input Clock or CAN be output synchronous to the output Clock When output synchronous to the input Clock the samples are accompanied by a data valid flag to indicate which samples are valid and which are invalid. When output synchronous to the output Clock the chip uses the internal 16 word FIFO to smooth the data. The output Clock CAN be provided externally, or CAN be generated within the chip using the internal Oscillator which is locked to the resampled data rate. By Texas Instruments
Part Manufacturer Description Datasheet Samples
GC3011-PQ Texas Instruments Digital Resampler 100-QFP
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