PCI ExpressTM PIPE X4 PHY

The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intels PHY Interface for the PCI Express Architecture rev. 1.0. It integrates a quad SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic Buffer and receiver detection, data serialization and deserialization for each lane. The quad SerDes in the GL9714 supports an effective serial Interface speed (2.5 Gb/s) of data bandwidth for each lane, intended for use in ultrahigh-speed bi-directional data transmission system. The GL9714 CAN also be externally configured for various combinations of lane number and parallel bus width which is flexible and suitable for x1, x2 or x4 lane implementation. It also supports four operational states for Power Management to minimize power consumption. For production and self-test purposes, the GL9714 provides BIST and an internal loopback capability. By Genesys Logic
GL9714 's PackagesGL9714 's pdf datasheet



GL9714 Pinout, Pinouts
GL9714 pinout,Pin out
This is one package pinout of GL9714,If you need more pinouts please download GL9714's pdf datasheet.

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