17-Bit TTL/GTLP Bus Transceiver With Buffered Clock

The GTLP16616 is a 17-bit registered Bus Transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) Clock output from the TTL CLKAB. The device provides a high speed Interface between cards operating at TTL Logic levels and a back- plane operating at GTLP Logic levels. High speed back- plane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus set- tling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchilds GTLP has internal edge-rate control and is pro- cess, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor
GTLP16616 's PackagesGTLP16616 's pdf datasheet

GTLP16616 Pinout, Pinouts
GTLP16616 pinout,Pin out
This is one package pinout of GTLP16616,If you need more pinouts please download GTLP16616's pdf datasheet.

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