17-Bit TTL/GTLP Synchronous Bus Transceiver With Buffered Clock

The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level transla- tion. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) Clock output from the TTL CLKAB. The device provides a high speed Interface between cards operating at TTL Logic levels and a Backplane operating at GTLP Logic levels. High speed Backplane operation is a direct result of GTLPs reduced output swing (<1V), reduced input thresh- old levels and output edge rate control. The edge rate con- trol minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchilds GTLP has internal edge-rate control and is pro- cess, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor
GTLP16617 's PackagesGTLP16617 's pdf datasheet

GTLP16617 Pinout, Pinouts
GTLP16617 pinout,Pin out
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