17-Bit LVTTL/GTLP Bus Transceiver With Buffered Clock

The GTLP17T616 is a 17-bit registered Bus Transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) Clock output from the LVTTL CLKAB. The device provides a high speed Interface between cards operating at LVTTL Logic levels and a Backplane operating at GTLP Logic levels. High speed Backplane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control mini- mizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor Logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Pro- cess, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor
Part Manufacturer Description Datasheet Samples
GTLP17T616MTD Rochester Electronics LLC Registered Bus Transceiver, GTLP Series, 1-Func, 17-Bit, True Output, BICMOS, PDSO56, 6.10 MM, MO-153, TSSOP-56
GTLP17T616MEA Rochester Electronics LLC Registered Bus Transceiver, GTLP Series, 1-Func, 17-Bit, True Output, BICMOS, PDSO56, 0.300 INCH, MO-118, SSOP-56
GTLP17T616 's PackagesGTLP17T616 's pdf datasheet
GTLP17T616MEA
GTLP17T616MTD




GTLP17T616 Pinout, Pinouts
GTLP17T616 pinout,Pin out
This is one package pinout of GTLP17T616,If you need more pinouts please download GTLP17T616's pdf datasheet.

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