36-Bit LVTTL/GTLP Universal Bus Transceiver

The GTLP36T612 is an 36-bit universal Bus Transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed Interface for cards operating at LVTTL Logic levels and a Backplane operating at GTLP Logic levels. High speed Backplane operation is a direct result of GTLPs reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gun- ning Transistor Logic (GTL) JEDEC standard JESD8-3. Fairchilds GTLP has internal edge-rate control and is Pro- cess, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor