GTLP-to-TTL 1:6 Clock Driver

The GTLP6C816 is a Clock Driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed Interface between cards operating at TTL Logic levels and a Backplane operating at GTLP Logic levels. High speed Backplane operation is a direct result of GTLPs reduced output swing (<1V), reduced input thresh- old levels and output edge rate control. The edge rate con- trol minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchilds GTLP has internal edge-rate control and is pro- cess, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor
GTLP6C816 's PackagesGTLP6C816 's pdf datasheet
GTLP6C816MTC




GTLP6C816 Pinout, Pinouts
GTLP6C816 pinout,Pin out
This is one package pinout of GTLP6C816,If you need more pinouts please download GTLP6C816's pdf datasheet.

GTLP6C816 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

GTLP6C816 Pb-Free GTLP6C816 Cross Reference GTLP6C816 Schematic GTLP6C816 Distributor
GTLP6C816 Application Notes GTLP6C816 RoHS GTLP6C816 Circuits GTLP6C816 footprint