Low Drive GTLP-to-LVTTL 1:6 Clock Driver

The GTLP6C817 is a low drive Clock Driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed Interface between cards operating at TTL Logic levels and a Backplane operating at GTLP Logic levels. High speed Backplane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels and output edge rate con- trol. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gun- ning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchilds GTLP has internal edge-rate control and is pro- cess, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor
GTLP6C817 's PackagesGTLP6C817 's pdf datasheet

GTLP6C817 Pinout, Pinouts
GTLP6C817 pinout,Pin out
This is one package pinout of GTLP6C817,If you need more pinouts please download GTLP6C817's pdf datasheet.

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