8-Bit LVTTL/GTLP Bus Transceiver

The GTLP8T306 is an 8-bit Bus Transceiver that provides LVTTL to GTLP signal level translation. The device pro- vides a high speed Interface between cards operating at LVTTL Logic levels and a Backplane operating at GTLP Logic levels. High speed Backplane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchilds GTLP has internal output edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different out- put levels and receiver thresholds. The GTLP output LOW level is typically less than 0.5V, the output HIGH level is 1.5V and the receiver threshold is 1.0V. By Fairchild Semiconductor
GTLP8T306 's PackagesGTLP8T306 's pdf datasheet
GTLP8T306MTC




GTLP8T306 Pinout, Pinouts
GTLP8T306 pinout,Pin out
This is one package pinout of GTLP8T306,If you need more pinouts please download GTLP8T306's pdf datasheet.

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