Radiation Hardened Synchronous Counter Corporation

The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous Counter features asynchronous reset and look-ahead carry Logic The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (P0 - P3) to load the Counter The data is latched to the outputs on the positive edge of the Clock input, CP. The HCTS161AMS has two count enable pins, PE and TE. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one Clock pulse and is used to enable the next cascaded stage to count. The HCTS161AMS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS161AMS is supplied in a 16 lead Ceramic atpack (K sufx) or a SBDIP Package (D sufx). By Intersil Corporation
HCTS161AMS 's PackagesHCTS161AMS 's pdf datasheet
HCTS161ADMSR
HCTS161AKMSR




HCTS161AMS Pinout, Pinouts
HCTS161AMS pinout,Pin out
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