18-bit Universal Bus Transceivers With 3-state Outputs - Hitachi Semiconductor

Data flow HD74ALVCH162500 in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low Logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the high to low transition of CLKAB. Output enable OEAB is active high. When OEAB is high, the B port outputs are active. When OEAB is low, the B port outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high, and OEBA is active low). Active bus hold circuitry is provided to hold unused or floating data inputs at a valid Logic level. All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot. By Renesas Technology
HD74ALVCH162500 's PackagesHD74ALVCH162500 's pdf datasheet

HD74ALVCH162500 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
HD74ALVCH162500 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

HD74ALVCH162500 Pb-Free HD74ALVCH162500 Cross Reference HD74ALVCH162500 Schematic HD74ALVCH162500 Distributor
HD74ALVCH162500 Application Notes HD74ALVCH162500 RoHS HD74ALVCH162500 Circuits HD74ALVCH162500 footprint
Hot categories