20-bit Universal Bus Driver With 3-state Outputs - Hitachi Semiconductor

This 20-bit universal bus driver HD74ALVCH162836 is designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE) input. The device operates in the transparent mode when the latch enable (LE) input is low. When LE is high, the A data is latched if the Clock (CLK) input is held at a high or low Logic level. If LE is high, the A data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid Logic level. All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot. By Renesas Technology