Octal D-type Flip-Flops (with Enable)

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the Clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the Clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G input. By Renesas Technology
HD74HC377 's PackagesHD74HC377 's pdf datasheet

HD74HC377 Pinout, Pinouts
HD74HC377 pinout,Pin out
This is one package pinout of HD74HC377,If you need more pinouts please download HD74HC377's pdf datasheet.

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