Bus Buffer Gate With 3–state Output / CMOS Logic Level Shifter

The HD74LV1GT125A has a bus Buffer Gate with 3state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logiclevel translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS Logic to 3.0 V CMOS Logic while operating at the High-Voltage power supply. Low voltage and high- speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. By Renesas Technology
HD74LV1GT125A 's PackagesHD74LV1GT125A 's pdf datasheet
HD74LV1GT125ACME
HD74LV1GT125AVSE

HD74LV1GT125A pdf datasheet download


HD74LV1GT125A Pinout, Pinouts
HD74LV1GT125A pinout,Pin out
This is one package pinout of HD74LV1GT125A,If you need more pinouts please download HD74LV1GT125A's pdf datasheet.

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