Dual Bus Buffer With 3–state Output CMOS Logic Level ShifterThe HD74LV2GT126A has dual bus Buffer with 3state output in a 8 pin package. Output is disable
when the associated output enable (OE) input is low. To ensure the high impedance state during power up
or power down, OE should be connected to GND through a pull-down resistor; the minimum value of the
resistor is determined by the current souring capability of the driver. The input protection circuitry on this
device allows over voltage tolerance on the input, allowing the device to be used as a logiclevel translato
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS Logic to 3.0 V CMOS Logic while
operating at the High-Voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life. By Renesas Technology
|
|
HD74LV2GT126A Pb-Free | HD74LV2GT126A Cross Reference | HD74LV2GT126A Schematic | HD74LV2GT126A Distributor |
HD74LV2GT126A Application Notes | HD74LV2GT126A RoHS | HD74LV2GT126A Circuits | HD74LV2GT126A footprint |