HEF4015B Dual 4-bit Static Shift Register

HEF4015B Dual 4-bit static Shift register The HEF4015B is a dual edge-triggered 4-bit static shift Register (serial-to-parallel converter). Each Shift register has a serial data input (D), a Clock input (CP), four fully buffered parallel outputs (O0 to O3 ) and an overriding asynchronous master reset input (MR). Information present on D is shifted to the first Register position, and all the data in the Register is shifted one position to the right on the LOW-to-HIGH transition of CP. A HIGH on MR clears the Register and forces O0 to O3 to LOW, independent of CP and D. Schmitt-trigger action in the Clock input makes the circuit highly tolerant to slower Clock rise and fall times.
By NXP Semiconductors
HEF4015B 's PackagesHEF4015B 's pdf datasheet
HEF4015BP DIP
HEF4015BT SO




HEF4015B Pinout, Pinouts
HEF4015B pinout,Pin out
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