HEF4020B 14-stage Binary Counter

HEF4020B 14-stage binary Counter The HEF4020B is a 14-stage binary ripple Counter with a Clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 , O3 to O13 ). The Counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all Counter stages and forces all outputs LOW, independent of the state of CP. Each Counter stage is a static toggle Flip-Flop A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V).
By NXP Semiconductors
HEF4020B 's PackagesHEF4020B 's pdf datasheet

HEF4020B Pinout, Pinouts
HEF4020B pinout,Pin out
This is one package pinout of HEF4020B,If you need more pinouts please download HEF4020B's pdf datasheet.

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