HEF4022B 4-stage Divide-by-8 Johnson Counter

HEF4022B 4-stage divide-by-8 Johnson Counter The HEF4022B is a 4-stage divide-by-8 Johnson Counter with eight spike-free decoded active HIGH outputs (O0 to O7 ), an active LOW output from the most significant Flip-Flop (O4-7 ), active HIGH and active LOW Clock inputs (CP0 , CP1 ) and an overriding asynchronous master reset input (MR). The Counter is advanced by either a LOW to HIGH transition at CP0 while CP1 is LOW or a HIGH to LOW transition at CP1 while CP0 is HIGH (see also function table). Either CP0 or CP1 may be used as Clock input to the Counter and the other Clock input may be used as a Clock enable input. When cascading Counters the O4-7 output, which is LOW while the Counter is in states, 4, 5, 6 and 7, CAN be used to drive the CP0 input of the next Counter A HIGH on MR resets the Counter to zero (O0 = O4-7 = HIGH; O1 to O7 = LOW) independent of the Clock inputs (CP0 , CP1 ). Automatic code correction of the Counter is provided by an internal circuit, following any illegal code the Counter returns to a proper counting mode within 11 Clock pulses.
By NXP Semiconductors
HEF4022B 's PackagesHEF4022B 's pdf datasheet

HEF4022B Pinout, Pinouts
HEF4022B pinout,Pin out
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