HEF4024B 7-stage Binary Counter

The HEF4024B is a 7-stage binary ripple Counter with a Clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6 ). The Counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all Counter stages and forces all outputs LOW, independent of CP. Each Counter stage is a static toggle Flip-Flop
By NXP Semiconductors
HEF4024B 's PackagesHEF4024B 's pdf datasheet

HEF4024B Pinout, Pinouts
HEF4024B pinout,Pin out
This is one package pinout of HEF4024B,If you need more pinouts please download HEF4024B's pdf datasheet.

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