HEF4029B Synchronous Up/down Counter, Binary/decade Counter

HEF4029B Synchronous up/down Counter binary/decade Counter The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade Counter with a Clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3 ), four parallel buffered outputs (O0 to O3 ) and an active LOW terminal count output (TC). Information on P0 to P3 is asynchronously loaded into the Counter while PL is HIGH, independent of CP. The Counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the Counter reaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW.
By NXP Semiconductors
HEF4029B 's PackagesHEF4029B 's pdf datasheet

HEF4029B Pinout, Pinouts
HEF4029B pinout,Pin out
This is one package pinout of HEF4029B,If you need more pinouts please download HEF4029B's pdf datasheet.

HEF4029B circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

HEF4029B Pb-Free HEF4029B Cross Reference HEF4029B Schematic HEF4029B Distributor
HEF4029B Application Notes HEF4029B RoHS HEF4029B Circuits HEF4029B footprint
Hot categories