HEF4527B MSI BCD Rate Multiplier

The HEF4527B is a BCD rate multiplier with two buffered rate outputs (O1 and O1), two buffered terminal count outputs (TC and TC), four BCD rate select inputs (SASB SCSD ), a common Clock input (CP), a preset input (PL), an overriding asynchronous clear input (CL), a strobe input (STR), a cascade input (CAS) and an active LOW count enable input (CE). The BCD rate multiplier provides an output pulse rate based upon the BCD input number. For example, if 6 is the BCD number, there will be six output pulses for every ten Clock input pulses. The output is clocked on the negative-going transition of the Clock When CE, STR, CAS, CL and PL are LOW, the rate pulses are available at the outputs O1 and O1the terminal count pulses at TC and TC.A HIGH on CL resets the Counter independent of all other input conditions and a rate of 10 pulses is available at O1 and O1 when SD is HIGH. When CE is HIGH, the Counter is disabled, the state of the outputs (O1O1 ) depend on the content of the Counter A HIGH on PL sets the Counter in the ,9, state and TC becomes HIGH.A HIGH on STR inhibits the outputs O1 and O1 . A HIGH on CAS forces the output O1 to HIGH, while the state of O1 depends on the inputs SA to SD (see lines 1 to 16 of function table). This device may be used to perform arithmetic operations. For the add mode and multiply mode see Figs 5 and 6. Schmitt-trigger action in the Clock input makes the circuit highly tolerant to slower Clock rise and fall times.
By NXP Semiconductors
HEF4527B 's PackagesHEF4527B 's pdf datasheet



HEF4527B Pinout, Pinouts
HEF4527B pinout,Pin out
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