256M SSTL_2 Interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ?? 16-bit ?? 4-bank/8-Mword ?? 8-bit ?? 4-bank/ 16-Mword ?? 4-bit ?? 4-bank

The HM5425161B the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) CAN be set enable or disable. By Elpida Memory, Inc.
HM5425161B 's PackagesHM5425161B 's pdf datasheet
HM5425801B
HM5425401B
HM5425161BTT-75A
HM5425161BTT-75B
HM5425161BTT-10-
HM5425801BTT-75A
HM5425801BTT-75B
HM5425801BTT-10-
HM5425401BTT-75A
HM5425401BTT-75B
HM5425401BTT-10




HM5425161B Pinout, Pinouts
HM5425161B pinout,Pin out
This is one package pinout of HM5425161B,If you need more pinouts please download HM5425161B's pdf datasheet.

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HM5425161B Application Notes HM5425161B RoHS HM5425161B Circuits HM5425161B footprint
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