256-Mbit Double-Data-Rate SDRAM

The 256 Mbit Double-Data-Rate SDRAM HYB25D256 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM The 256 Mbit Double-Data-Rate SDRAM uses a double- data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an Interface designed to transfer two data words per Clock cycle at the I/O pins. A single read or write access for the 256 Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one Clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. By Qimonda
HYB25D256 's PackagesHYB25D256 's pdf datasheet
HYB25D256400CT-
HYB25D256800CT-
HYB25D256160CT-
HYB25D256800CTL-
HYB25D256400CC-
HYB25D256800CC-
HYB25D256160CC-
HYI25D256800CT-
HYI25D256160CT-
HYI25D256800CC-
HYI25D256160CC-
HYB25D256800CE-




HYB25D256 Pinout, Pinouts
HYB25D256 pinout,Pin out
This is one package pinout of HYB25D256,If you need more pinouts please download HYB25D256's pdf datasheet.

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HYB25D256 Application Notes HYB25D256 RoHS HYB25D256 Circuits HYB25D256 footprint
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