512-Mbit Double-Data-Rate SDRAM

The 512-Mbit Double-Data-Rate SDRAM is a highspeed The 512-MbitDouble-Data-RateSDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912bits. It is internally configured as a quad-bank DRAM The 512-MbitDouble-Data-RateSDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an Interface designed to transfer two data words per Clock cycle at the I/O pins. A single read or write access for the 512-MbitDouble-Data-RateSDRAM effectively consists of a single 2n-bit wide, one Clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the Memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. By Infineon Technologies Corporation