512-Mbit Double-Data-Rate SDRAM

The 512-Mbit Double-Data-Rate SDRAM HYB25D512800D is a high-speed CMOS, dynamic random-access memory containing 536, 870, 912 bits. It is internally configured as a quad-bank DRAM The 512-Mbit Double-Data-Rate SDRAM uses a double- data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an Interface designed to transfer two data words per Clock cycle at the I/O pins. A single read or write access for the 512-Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one Clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. By Qimonda
HYB25D512800D 's PackagesHYB25D512800D 's pdf datasheet
HYB25D512160DC-5
HYB25D512160DT-5
HYI25D512800DE-5
HYI25D512160DE-5
HYI25D512800DF-5
HYI25D512160DF-5
HYI25D512800DE-6
HYI25D512160DE-6
HYI25D512800DF-6
HYI25D512160DF-6
HYB25D512400DT-5
HYB25D512800DT-5
HYB25D512800DC-5
HYB25D512160DC-6
HYB25D512160DT-6
HYB25D512400DT-6
HYB25D512800DC-6
HYB25D512800DT-6
HYI25D512160DT-5
HYI25D512160DC-5
HYI25D512160DT-6
HYI25D512160DC-6
HYB25D512800DF-5
HYB25D512160DF-5
HYB25D512400DE-5
HYB25D512160DE-5
HYB25D512400DF-5
HYB25D512800DE-5
HYB25D512160DEL-6
HYB25D512160DF-6
HYB25D512400DE-6
HYB25D512800DEL-6
HYB25D512160DE-6
HYB25D512800DE-6
HYB25D512400DF-6
HYB25D512800DF-6




HYB25D512800D Pinout, Pinouts
HYB25D512800D pinout,Pin out
This is one package pinout of HYB25D512800D,If you need more pinouts please download HYB25D512800D's pdf datasheet.

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