256 Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant

The 256 Mbit Double-Data-Rate SDRAM HYB25DC256800C is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an Interface designed to transfer two data words per Clock cycle at the I/O pins. A single read or write access for the 256 Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one Clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins By Qimonda
HYB25DC256800C 's PackagesHYB25DC256800C 's pdf datasheet
HYB25DC256800CE-
HYB25DC256160CE-
HYB25DC256800CF-
HYB25DC256160CF-




HYB25DC256800C Pinout, Pinouts
HYB25DC256800C pinout,Pin out
This is one package pinout of HYB25DC256800C,If you need more pinouts please download HYB25DC256800C's pdf datasheet.

HYB25DC256800C circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

HYB25DC256800C Pb-Free HYB25DC256800C Cross Reference HYB25DC256800C Schematic HYB25DC256800C Distributor
HYB25DC256800C Application Notes HYB25DC256800C RoHS HYB25DC256800C Circuits HYB25DC256800C footprint
Hot categories