256-Mbit Double-Data-Rate SGRAM

The 256-Mbit Double-Data-Rate SGRAM HYB25DC256803C is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM The 256-Mbit Double-Data-Rate SGRAM uses a double-data-rate architecture to achieve high-speed operation. The double- data-rate architecture is essentially a 2n prefetch architecture with an Interface designed to transfer two data words per Clock cycle at the I/O pins. A single read or write access for the 256-Mbit Double-Data-Rate SGRAM effectively consists of a single 2n-bit wide, one Clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. By Qimonda
HYB25DC256803C 's PackagesHYB25DC256803C 's pdf datasheet
HYB25DC256803CE-4
HYB25DC256803CE-5
HYB25DC256803CE-6
HYB25DC256163CE-4
HYB25DC256163CE-5
HYB25DC256163CE-6
HYB25DC256803CF-4
HYB25DC256803CF-5
HYB25DC256803CF-6
HYB25DC256163CF-4
HYB25DC256163CF-5
HYB25DC256163CF-6




HYB25DC256803C Pinout, Pinouts
HYB25DC256803C pinout,Pin out
This is one package pinout of HYB25DC256803C,If you need more pinouts please download HYB25DC256803C's pdf datasheet.

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HYB25DC256803C Application Notes HYB25DC256803C RoHS HYB25DC256803C Circuits HYB25DC256803C footprint
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