Mulitplier And Zero Delay Buffer

The ICS2402 is a high-performance Zero Delay Buffer (ZDB) which integrates IDTs proprietary Analog/Digital Phase-Locked Loop (PLL) techniques. The chip is part of the IDT ClockBlocks family and was designed as a performance upgrade to meet todays higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input Clock aligns with the rising edges of both output Clocks giving the appearance of no delay through the device. The ICS2402 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data Communications to graphics Video By allowing off-chip feedback paths, the device CAN eliminate the delay through other devices. 8-pin SOIC package Available in Pb (lead) free package Absolute jitter 100 ps Propagation Delay of 600 ps Output multiplier of 2X Output Clock frequency up to 80 MHz CAN recover degraded input Clock duty cycle Output Clock duty cycle of 45/55 Full CMOS Clock swings with 25 mA drive capability at TTL levels Advanced, low power CMOS process Operating voltage of 3.3 V or 5 V By Integrated Device Technology
ICS2402 's PackagesICS2402 's pdf datasheet

ICS2402 Pinout, Pinouts
ICS2402 pinout,Pin out
This is one package pinout of ICS2402,If you need more pinouts please download ICS2402's pdf datasheet.

ICS2402 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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ICS2402 Pb-Free ICS2402 Cross Reference ICS2402 Schematic ICS2402 Distributor
ICS2402 Application Notes ICS2402 RoHS ICS2402 Circuits ICS2402 footprint