Clock Divider

The ICS542 is cost effective way to produce a high-quality Clock output divided from a Clock input. The chip accepts a Clock input up to 156 MHz. Using proprietary Phase-Locked Loop (PLL) techniques, the device produces a divide by 2, 4, 6, 8, 12, or 16 of the input Clock There are two outputs on the chip, one being a low-skew divide by two of the other. 8-pin SOIC package Low-cost Clock divider Low-skew (500 ps) outputs. One is /2 of the other Easy to use with other generators and Buffers Input Clock frequency up to 156 MHz Output Clock duty cycle of 45/55 Power-down turns off chip Output Enable Full CMOS Clock swings with 25 mA drive capability at TTL levels Advanced, low power CMOS process Operating voltage of 3.3 or 5 V By Integrated Device Technology
ICS542 's PackagesICS542 's pdf datasheet
ICS542M SOIC
ICS542MI SOIC
ICS542MILF SOIC
ICS542MILFT SOIC
ICS542MIT SOIC
ICS542MLF SOIC
ICS542MLFT SOIC
ICS542MT SOIC




ICS542 Pinout, Pinouts
ICS542 pinout,Pin out
This is one package pinout of ICS542,If you need more pinouts please download ICS542's pdf datasheet.

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