Zero Delay, Low Skew Buffer

The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay Buffer for high speed applications. Based on IDTs proprietary low jitter Phase locked loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input Clock External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element. Packaged in 8-pin narrow SOIC Available in Pb (lead) free package Zero input-to-output delay Four 1X outputs Output to output skew is less than 150 ps Output Clocks up to 160 MHz at 3.3 V External feedback path for output edge placement Spread Smart technology works with spread spectrum Clock Generators Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V Advanced, low power, sub-micron CMOS process Operating voltage from 3.0 to 5.5 V Industrial temperature version available By Integrated Device Technology
ICS574 's PackagesICS574 's pdf datasheet
ICS574M SOIC
ICS574MI SOIC
ICS574MILF SOIC
ICS574MILFT SOIC
ICS574MIT SOIC
ICS574MLF SOIC
ICS574MLFT SOIC
ICS574MT SOIC




ICS574 Pinout, Pinouts
ICS574 pinout,Pin out
This is one package pinout of ICS574,If you need more pinouts please download ICS574's pdf datasheet.

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