PLL Building Block

The ICS663 is a low cost Phase-Locked Loop (PLL) designed for Clock synthesis and synchronization. Included on the chip are the phase detector, Charge Pump Voltage Controlled Oscillator (VCO) and an output Buffer Through the use of external reference and VCO dividers (implemented with the ICS674-01, for example), the user CAN easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device CAN also be used independently. This enables the configuration of other PLL circuits. For example, the ICS663 phase detector CAN be used to control a VCXO circuit such as the MK3754. For applications requiring Power Down or Output Enable features, please refer to the ICS673-01. Packaged in 8-pin SOIC (Pb free) Output Clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V) External PLL loop Filter enables configuration for a wide range of input frequencies Ability to accept an input Clock in the kHz range (video HSYNCH, for example) 25 mA output drive capability at TTL levels Lower power CMOS process +3.3 V 5% or +5 V 10% operating voltage Used along with the ICS674-01, forms a complete PLL circuit Phase detector and VCO blocks CAN be used independently for other PLL configurations Industrial temperature version available For better jitter performance, use the MK1575 By Integrated Device Technology
ICS663 's PackagesICS663 's pdf datasheet
ICS663M SOIC
ICS663MI SOIC
ICS663MILF SOIC
ICS663MILFT SOIC
ICS663MIT SOIC
ICS663MLF SOIC
ICS663MLFT SOIC
ICS663MT SOIC




ICS663 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
ICS663 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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