DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: Max frequency supported = 266MHz (DDR 533) Low skew, low jitter PLL Clock Driver I2C address selection for dual Buffer application I2C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs 3.3V toerant CLK_INT input By Integrated Device Technology
ICS93777 's PackagesICS93777 's pdf datasheet
ICS93777BF SSOP
ICS93777BFIT SSOP
ICS93777BFLF SSOP
ICS93777BFLFT SSOP
ICS93777BFT SSOP




ICS93777 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
ICS93777 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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