2.5 Single-Ended-to-SSTL_2 Clock Driver (33MHz - 233MHz)

Low skew, low jitter PLL Clock Driver 1 to 10 differential Clock Distribution (SSTL_2) Feedback pin for input to output synchronization PD# for Power Management Spread Spectrum tolerant inputs By Integrated Device Technology
ICS95V157A 's PackagesICS95V157A 's pdf datasheet
ICS95V157AG TSSOP
ICS95V157AGI TSSOP
ICS95V157AGIT TSSOP
ICS95V157AGLF TSSOP
ICS95V157AGLFT TSSOP
ICS95V157AGT TSSOP




ICS95V157A Pinout, Pinouts
ICS95V157A pinout,Pin out
This is one package pinout of ICS95V157A,If you need more pinouts please download ICS95V157A's pdf datasheet.

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