2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)

The ICS95V857 is a zero delay Buffer that distributes a differential Clock input pair (CLK_INC, CLK_INT) to ten differential pair of Clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback Clock output (FB_OUT, FB_OUTC). The Clock outputs are controlled by the input Clocks (CLK_INC, CLK_INT), the feedback Clocks (FB_INT, FB_INC) the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential Clock outputs are Tri-Stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. By Broadcom Corp.
ICS95V857 's PackagesICS95V857 's pdf datasheet



ICS95V857 Pinout, Pinouts
ICS95V857 pinout,Pin out
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