2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)

The ICS95V857 is a zero delay Buffer that distributes a differential Clock input pair (CLK_INC, CLK_INT) to ten differential pair of Clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback Clock output (FB_OUT, FB_OUTC). The Clock outputs are controlled by the input Clocks (CLK_INC, CLK_INT), the feedback Clocks (FB_INT, FB_INC) the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential Clock outputs are Tri-Stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. By Broadcom Corp.
ICS95V857 's PackagesICS95V857 's pdf datasheet

ICS95V857 Pinout, Pinouts
ICS95V857 pinout,Pin out
This is one package pinout of ICS95V857,If you need more pinouts please download ICS95V857's pdf datasheet.

ICS95V857 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

ICS95V857 Pb-Free ICS95V857 Cross Reference ICS95V857 Schematic ICS95V857 Distributor
ICS95V857 Application Notes ICS95V857 RoHS ICS95V857 Circuits ICS95V857 footprint