DB1900G: CPU Host Bus, PCI Express And Fully-Buffered DIMM Clocking

Features: Power up default is all outputs in 1:1 mode DIF_(16:0) CAN be gear-shifted from the input CPU Host Clock DIF_(18:17) CAN be gear-shifted from the input CPU Host Clock Spread spectrum compatible Supports output Clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode VDDA controlled power down mode By Integrated Device Technology
ICS9FG1901 's PackagesICS9FG1901 's pdf datasheet
ICS9FG1901CKLF VFQFPN
ICS9FG1901CKLFT VFQFPN
ICS9FG1901EKLF VFQFPN
ICS9FG1901EKLFT VFQFPN




ICS9FG1901 Pinout, Pinouts
ICS9FG1901 pinout,Pin out
This is one package pinout of ICS9FG1901,If you need more pinouts please download ICS9FG1901's pdf datasheet.

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