DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Output Features: Low skew, low jitter PLL Clock Driver Max frequency supported = 400MHz (DDRII 800) I2C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Programmable skew through SMBus Frequency defect control thorugh SMBus Individual output control programmable through SMBus By Integrated Device Technology
ICS9P935 's PackagesICS9P935 's pdf datasheet
ICS9P935AFLF SSOP
ICS9P935AFLFT SSOP
ICS9P935AGLF TSSOP
ICS9P935AGLFT TSSOP




ICS9P935 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
ICS9P935 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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