DDR 13-Bit To 26-Bit Registered Buffer

The 13-bit-to-26-bit ICSSSTVF16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential Clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVF16859 supports low- power standby operation. A Logic level Low at RESET# assures that all internal Registers and outputs (Q) are reset to the Logic Low state, and all input receivers, data (D) and Clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid Logic state because VREF may not be stable during power-up. By Broadcom Corp.
ICSSSTVF16859 's PackagesICSSSTVF16859 's pdf datasheet



ICSSSTVF16859 Pinout, Pinouts
ICSSSTVF16859 pinout,Pin out
This is one package pinout of ICSSSTVF16859,If you need more pinouts please download ICSSSTVF16859's pdf datasheet.

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